Employment history and professional experience

May 2001 - Present: Company "Elvees" <www.elvees.ru/en/index.html> Leading Engineer.

• RISC+DSP cores in one chip. OMAP technology chip. System On Chip designing technology
• Synthesis digital circuit from Verilog description. Simulate design at logic and netlist level using SDF-file from topology.
• Verilog behavioral and projects restructuring for best synthesis result.
• Serial port, Link port and UART synthesis and creating testing schedule.
• Static Timing Analysis of all chip
• Creating Layout for all chip except Power and Verification stage. Clock tree and reset tree designing. Physical Synthesis
• Synthesis whole chip (SOC) at 0.8, 0.5, 0.25, 0.18 micron http://multicore.ru/en/project.shtml
• Have 6 successfully projects: MC_12S, MC_23S ... (see Project form page)

• Development of the system of Automatic Cell Characterization (ACC) for ASIC Library.
• ASIC Library Design (core and pads)
  [channelles gate array 1592XMx - 100000 EG; 1.2 micron technology] www.angstrem.ru/bmk.htm
• Participated in creation of topology of cells of a core and pads. Perform LVS (layout versus schematic).
• Development of the test circuits permitting to certify the created library of cells and macroblocks. Building of complicated testbenches using VHDL/Verilog for the design. Select test strategy.
• Development of the design flow in the OrCAD environment (with further translation of the circuit on the platform Cadence using EDIF). Technical documentation at all design flow stages.
• Prelayout and Postlayout simulation of the circuit, using SDF-file in Express (OrCAD) and Verilog-XL (Cadence).
• Shared in testing of wafers and microcircuit on HP82000 tester.
• Have 2 successfully projects: 1592XM1-001 (~50000 EG) and 1592XM4-001 (~1000 EG). Both are for military application.

• 7 years of experience in HDL languages as VHDL (using Vital) / Verilog.
• Opus DB & SKILL (Cadence) programming – 1.5 year.
• ASIC library design.
• Synthesis digital design from VHDL / Verilog description in Synopsys (DA, DC, LC, PT), Leonardo Spectrum, Build Gates.
• Development digital circuit in OrCAD (Capture, Express, Spice) – 3 years.
• Development ASIC digital circuit in Cadence – 7 years.
• Prelayout and Postlayout simulation of the circuit, using SDF-file in Verilog-XL / NC-Sim (Cadence) and Express (OrCAD).
• CAD systems: Synopsys (Design Analyzer, Library Compiler, Prime Time), Cadence (Virtuoso; Verilog-XL, NC-Verilog, Pearl; Analog Artist; Synergy, Spice, SOC Encounter, LDV); OrCAD.
• SOC designing, building ClockTree, LVS (layout versus schematic).
• Compilation testbench for digital design.
• 3 years Assembler Z80, MCS51 programming.
• Development FPGA digital circuit in Altera MAX-plus II.
• Programming language: UNIX Shell Script (sh, ksh), Pascal, BASIC.
• OS: Windows 9X/NT/2000,XP, Unix (Solaris), Linux;