ASIC (channelless gate-array 1592XMx) designing.

Views for trigger (as for example):

Schematic

transistor-level schematic

Topology

topology of DFBTNB trigger

VHDL (or Verilog) description

Trigger's VHDL (using Vital) - description



And as present, our 1592XM4 (10 000 Equivalent Gates) picture:
/ It design for testing CORE and PAD librarys: 1592XM4-T05, that I designed.
In the cristal's right top corner You can see the static-ROM block /

1592XM4-T05 design


1592XM1 is 100 000 EG cristal:

1592XM1-T02 design

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